The present invention generally relates to phase detectors, and more specifically to direction sensitive phase detectors.
Phase detectors are found in numerous applications of all modern technologies. They are widely used in areas of electronics and in different fields of communication, in particular the field of telecommunication.
Basically, a phase detector is an arrangement for measuring a phase difference between two input signals. In a typical application, the phase detector is used in a phase-locked loop (PLL). A phase-locked loop is generally a circuit for synchronizing an output signal of the loop with an input reference signal in frequency as well as in phase, and it is often used in retiming and frequency synthesization applications. In order to accomplish the synchronization of the reference signal and the loop output signal, a phase detector is required for continuously measuring the phase difference between the two signals, and the measured phase difference is utilized for controlling the frequency of the loop output signal.
FIG. 1 is a schematic block diagram of a conventional phase-locked loop. The PLL 10 basically includes a phase detector (PD) 13, a loop filter (LF) 14 and an output clock signal source such as a voltage-controlled oscillator (VCO) 15. The phase detector 13 is generally responsive to the output signal (V) of the VCO 15 and an incoming reference clock signal (R) provided by a reference clock signal source 11 for generating a phase difference representing signal. The loop filter 14 averages or integrates the phase difference representing signal to produce a control voltage (VC) for the VCO 15. For generality, it should be understood that the PLL may very well be associated with frequency dividers, for example a first divider 12 for the reference clock signal from the reference clock source 11 and a second divider 16 for the output clock signal of the VCO 15 in the feedback loop.
The synchronization is achieved by frequency correction of the loop output signal in response to the phase difference measured by the phase detector. In the synchronized state, also referred to as the locked state or steady state, there is a predefined mandatory phase relation between the VCO output clock signal and the input reference clock signal, and there is generally no average frequency offset between the signals. However, if there is an instantaneous phase jump, or if a phase difference starts to build up, e.g. due to a frequency offset between the loop output signal and the reference signal, the phase-locked state is lost and the inherent control mechanism of the PLL strives to eliminate the frequency offset and find the phase-locked state again.
Of special interest is the impact of different phase detector (PD) choices on the overall PLL performance such as lock-in procedure and range, static phase error at lock and sensitivity to input clock anomalies. Two phase detectors are commonly used, the simple XOR gate (digital multiplier) and the direction sensitive phase-frequency detector (PFD).
Digital Multiplier
For the XOR gate based PLL, lock acquisition is totally unaided. Lock acquisition starts in a random direction until the proper direction is stumbled onto and ends when the loop filter has been charged to proper voltage for nominal output frequency and zero phase error at the phase detector input. If the reference clock behaves abnormal with a large content of harmonics to the fundamental reference clock frequency, a PLL utilizing an XOR gate PD may falsely lock to a harmonic since it has no frequency selection capability. On the other hand the averaging nature of the XOR gate PD reduces the PLL sensitivity to noise and other disturbances.
Phase Frequency Detector
However, to obtain a more structured lock acquisition procedure rather than pure random operation, it is advisable to use a phase frequency detector (PFD), which differentiates between frequency and pure phase mismatches and introduces so-called direction sensitivity. The phase frequency detector is a multi-state detector, which is capable not only of measuring the magnitude of the phase difference, but also of indicating the lead/lag relation between the clock signals. In this way, the frequency of the loop output signal can generally be altered directly in the right direction without losing valuable time.
FIG. 2 is a schematic state diagram representation of state machine for a conventional phase frequency detector. The PFD state machine has four different states denoted 00/LL, 01/LH, 10/HL and 11/HH, and alternates between two distinct control loops depending on the lead/lag relation between the clock signals. The transition conditions are associated with the signal states of the input clock signals to the PFD state machine, and indicated along the transition lines in the state diagram.
FIG. 3 is a circuit diagram of a typical implementation of the PFD state machine of FIG. 2. The PFD implementation 20 is based on D flip-flops (DFFs) 21, 22 and a NAND gate 23. The phase detector is triggered by positive edge transitions, and fed by a supply voltage (VCC). The phase detector has a step-up frequency output terminal (retard phase terminal) uR and a step-down frequency output terminal (advance phase terminal) uV. As indicated in FIG. 2, the physical phase detector output voltages uV and uR, coded as L (Low) or H (High), are associated with the state variables QV and QR, respectively.
In the PLL, the frequency of the loop output signal is adjusted when the loop filter integrator is charged or discharged by the phase frequency detector output. Irrespective of the initial state of the PFD, only the DFF that receives a positive edge transition on the associated PFD input will be active with a high Q output. Whenever one of the input clocks lag in frequency, only one PFD output terminal is active to signal the direction of the regulation to speed up the clock with lower frequency. For example, if the reference clock is ahead of the VCO clock, then uR is high (H) with UV constantly low (L) corresponding to the state 01/LH in the state diagram of FIG. 2, and the loop filter integrator is charged, thus increasing the VCO control voltage and the VCO output frequency. For a lagging reference clock the situation is reversed and uR is low (L) with uV high (H) corresponding to the state 10/HL so that the loop filter integrator is drained of charge and the VCO output frequency is lowered. Due to the asynchronous implementation there is an intermediate state 11/HH that is implicitly formed from the finite reset time of the state variables (DFFs) in the transitions to the ground state 00/LL. Missing clock pulses in the reference clock will be interpreted by the PFD as a frequency mismatch, and to prevent the PLL from reacting with abrupt output frequency changes a resonant circuit, a so-called Q-tank, is normally arranged prior to the reference clock input of the PFD.
Compared to a PLL based on a multiplier phase detector that averages the phase difference with no built in directivity, a more well defined lock acquisition procedure is obtained with a direction sensitive PFD type detector. However, conventional PFD type detectors suffer from problems with so-called phase inversion.
Phase Inversion
For a PLL based on a direction sensitive PFD detector there are always at least two different trajectories or paths that lead to phase lock from a given initial phase relation between the reference clock and the loop output clock. Since the loop output clock may be advanced or retarded the phase difference (xcex8e) is reduced to zero either the shortest distance (xcex8e) or the longer distance (360xc2x0xe2x88x92xcex8e) from the complementary direction. For the common phase frequency detector that has a linear range including both possibilities, a disturbance may shift the phase detector state such that the control system is forced to minimize the very large complementary phase error producing a large amount of output jitter during such a relock acquisition. For example, such a phase inversion situation may occur during reference clock loss.
FIG. 4 is a schematic timing diagram illustrating a phase inversion situation during reference clock loss. The timing diagram illustrates a reference clock R and a loop output signal V tracking the reference clock. Also shown in the timing diagram are the output signals uV and uR of the PFD state machine. As can be seen from timing diagram, the PFD state machine is initially in the ground state 00 waiting for a next positive edge transition. As the first positive transition of the reference clock R occurs, uR goes high and the PFD state machine transitions into the state 01 in which it starts measuring the phase difference between the two clocks R and V. As the first positive transition of the loop output clock V occurs, uV goes high and the PFD state machine transitions into the reset state 11. In a typical application, the output signals uV and uR of the PFD state machine drives the frequency of the loop output clock V during the entire phase difference measurement interval between the positive transition of R and the positive transition of V. Alternatively, in an all-digital control system, the phase difference xcex8e is extracted at the end of the measurement interval and subsequently used in the regulation of the loop output clock V. After a finite reset time trst, the PFD state machine is back in its ground state 00 where it awaits the next phase difference measurement, and so on. Apparently, the state machine operates in the state trajectory 00-01-11-00. However, after some time, the reference clock R is temporarily lost. After being reset to its ground state 00 the second time, the state machine now transitions into the alternative state 10 since the loop output clock V goes high (indicated by a dashed line) before the reference clock R, which is now missing. Once the reference clock R has returned, uR goes high and the PFD state machine transitions into the reset state 11, and subsequently into the ground state 00 where it awaits the next phase difference measurement. However, now the state machine is put into the reset state by a positive R transition instead of a positive V transition. This means that the state machine operates in the alternative state trajectory 00-10-11-00 and the phase information has shifted to the complementary (360xc2x0xe2x88x92xcex8e), which is much larger than the initial phase error measured before the phase inversion.
Although the phase inversion problem mainly is described in relation to missing reference clock pulses, it is important to understand that other perturbations and faults such as an anomalous loop output clock may also cause phase inversion.
The present invention overcomes these and other drawbacks of the prior art arrangements.
U.S. Pat. No. 5,191,239 issued on Mar. 2, 1993 to Rogers discloses a reset gate for a phase frequency detector (PFD) in a phase-locked loop for handling an internal PFD race condition.
U.S. Pat. No. 5,691,656 issued on Nov. 25, 1997 to Sandusky is related to the direction sensitivity of phase detector and discloses a latching phase detector. The phase detector includes a reference signal differentiator and an input signal differentiator. Each differentiator has a corner frequency that is easily adjustable to block DC and low frequency offsets. The corner frequency can be adjusted to result in a precise (nxcfx80)/2 latching phase detector, which detects whether the phase difference is greater or less than (nxcfx80)/2 where n is an integer between 1 and 4.
U.S. Pat. No. 5,963,058 issued on Oct. 5, 1999 to Thomas discloses a phase frequency detector, which includes circuitry of transistors configured to adjust an amount of overlap of an up signal and a down signal based upon the magnitude of a phase delay between two clock signals. The circuitry is configured to produce a PFD output signal in which the sign of the phase delay indicated remains the sign of the phase delay between the applied clock signals even as the magnitude of the phase delay approaches 360xc2x0.
U.S. Pat. No. 5,920,207 issued on Jul. 6, 1999 to Suresh discloses an asynchronous phase detector. The phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop, and the state machine is implemented with logic that provides for optimal sensitivity and minimal dead zone.
It is a general object of the present invention to provide a robust phase detector, which effectively prevents phase inversion while maintaining direction sensitivity.
In particular, it is desirable to provide the phase detector in a true asynchronous design.
These and other objects are met by the invention as defined by the accompanying patent claims.
The present invention is based on the recognition that conventional direction sensitive phase detectors are susceptible to phase inversion when the reset state has a duration that is smaller than the phase error between the reference clock and the loop output clock, thus not properly masking the complementary state. The general idea according to the invention is to design the phase detector state machine with a reset state that is released only when both phase detector input signals have a common predetermined signal state.
In this way, the complementary phase error is properly masked and the phase detector range is effectively reduced to xe2x88x92180xc2x0 less than xcex8e less than 180xc2x0, while still maintaining the direction sensitivity. The alternative state trajectory is simply not available any more since the complementary phase error, xcex8ec=360xc2x0xe2x88x92xcex8e greater than 180xc2x0, is larger than half a period, which exceeds the detection range, and is automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector is shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.
The phase detector state machine configured with the proposed logic reset state is preferably implemented as a true asynchronous state machine instead of operating with the reset and recovery characteristics of digital flip flops. Designing an asynchronous state machine based on implicitly formed memory elements gives near ideal operation.
The invention offers the following main advantages:
The susceptibility to phase inversion is eliminated, while still maintaining direction sensitivity; and
Reduced lock-acquisition time.
Other advantages offered by the present invention will be appreciated upon reading of the below description of the embodiments of the invention.